A Reference-Waveform Oversampling Technique in a Fractional-N ADPLL

This article presents a low-power fractional- ${N}$ all-digital phase-locked loop (ADPLL) employing reference-waveform oversampling (ROS) phase detector (PD) that increases its effective rate four times, thus leading to lower jitter and settling time. The proposed ROS-PD adopts bottom-plate sampling with voltage zero-forcing technique, which yields high power efficiency supports fractional compensation in the domain through programmable DAC. PD output is then amplified by low-noise gated amplifier digitized successive approximation register analog-to-digital converter (SAR-ADC). Leveraging benefits of digital architecture, gain mismatches from waveform estimator are calibrated means an LMS algorithm, consequently lowering spurs. ADPLL implemented TSMC 28-nm LP CMOS. prototype generates 2.0–2.3-GHz carrier rms 414 fs while consuming only 1.15 mW. corresponds state-of-the-art FoM jitter ?247 dB mode. Due wide (largely linear) monotonic range notation="LaTeX">$4\times $ 48-MHz reference, without any additional circuitry, can settle within notation="LaTeX">$3~\mu \text{s}$ face 70-MHz frequency step.